Layout Design Intern (Summer 2026), Ahuntsic North

How You Will Make an Impact

Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade‑offs and layout strategies for high‑speed circuits Develop custom layouts for advanced analog and mixed‑signal blocks, following structured methodologies for floorplanning, placement, and routingExecute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability Support continuous improvement by exploring new layout tool features, flows, and processes to enhance efficiency and productivityCollaborate closely with circuit designers and layout engineers to identify and resolve layout‑related risks early in the design cycle Provide clear status updates and actively participate in team meetings, design discussions, and knowledge‑sharing activities Requirements

Currently pursuing a degree in Electrical Engineering or a related field Hands‑on experience with custom analog and mixed‑signal layout design in deep sub‑micron complementary metal‑oxide semiconductor (CMOS) technologies Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerationsExperience creating custom layouts for analog or mixed‑signal blocks such as operational amplifiers or current mirrors Familiarity with semiconductor manufacturing processes and foundry design rules Experience using industry‑standard layout tools such as Cadence Virtuoso and Siemens Calibre Ability to interpret and debug DRC and LVS reports effectivelyNice to Haves

Exposure to high‑speed data converter or phase‑locked loop (PLL) layout design Familiarity with bipolar CMOS (BiCMOS) technologies Scripting experience using PERL or SKILL to support layout automation or productivity improvements Experience collaborating in cross‑functional hardware design teamsStrong analytical skills with the ability to proactively identify layout‑sensitive circuit structures Pay and Benefits

Pay Range: The hourly pay rate for this position is $25.00–$34.00. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. The pay range information provided in this posting pertains specifically to the primary location listed in case multiple locations are available.Benefits include: Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, vacation pay as required by applicable laws, and other competitive compensation. EEO Statement

Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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