Lead Digital Design Engineer Role In Ottawa

Ciena is seeking a Lead Digital Design Engineer to innovate in high-speed connectivity projects. This senior position focuses on ASIC design and guiding junior engineers in a team-oriented setting. Your role will involve implementing ASIC designs while leveraging over 10 years of experience in complex designs and working with C/C++ and System Verilog. You'll contribute significantly to the development of the Forward Error Correction (FEC) IP while mentoring newer team members and participating in comprehensive design reviews. Key Responsibilities: Collaborate across teams to ensure design specifications are met Deliver high-quality RTL and/or C source code for multiple projects Conduct thorough simulations and regression testing of code Lead design reviews, including timing and layout assessments Mentor junior verification engineers to enhance team performance Requirements: Bachelor's degree in Electrical or Computer Engineering Minimum of 10 years in related ASIC/FPGA design Robust experience with C/C++, synthesis tools, and HLS methodologies Familiarity with bug tracking tools and GIT A solid understanding of FEC and DSP concepts Play a critical role in Ciena’s mission while fostering collaboration and innovation in high-speed networking. Apply on Kit Job: kitjob.ca/job/2p9lf3