FPGA Design Engineer (Ottawa)

Position Summary Stefanini Group is hiring an FPGA Design Engineer with Radio experience for an onsite role in Ottawa, Ontario, Canada. Contact: Prakhar Goel, , Benefits - 10 days PTO (80 hours, accrual based) - 9 holidays on average throughout the year - 3 personal days Ideal Candidate FPGA designer engineer with Radio experience working with 4G/5G radios, 7+ years, heavy SystemVerilog/RTL experience, no VHDL. Tools and Experience - Altera Quartus - MATLAB/Simulink for modeling AXI and Ethernet protocols - Advanced high‑speed experience is desirable Responsibilities - Work on complex problems and provide creative solutions using independent judgment. - Stay informed on industry trends and communicate vision for long‑term strategy. - Conduct research, contribute to evaluations, project plans and budgets. - Consult on critical projects impacting long‑term goals. - Lead teams, give technical guidance, communicate with senior management. - Set standards and achieve cost targets through design choices and component selection. - Perform competitive analysis and seek customer input. - Define functional specifications for entire system under consultative direction. What You'll Do - Design FPGA IP architecture for 4G/5G Radio Units. - Contribute to system‑level design aligned with 3GPP and O‑RAN specifications. - Implement complex RTL blocks in Verilog or SystemVerilog. - Optimize FPGA resource utilization and ensure timing closure. Validation & Testing - Define and execute verification plans using UVM and advanced techniques. - Perform simulation and system‑level FPGA validation. Collaboration - Work with Radio Unit development teams for integration. - Partner with software teams for hardware‑software interoperability. - Mentor junior engineers and participate in technical reviews. Essential Requirements - Proven experience in FPGA design and RTL development. - Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing. - Familiarity with JESD204B/C, Ethernet, PCIe, AXI, and high‑speed SERDES. - Proficiency with Quartus, Vivado, MATLAB/Simulink, HDL Coder. - Knowledge of UVM and verification methodologies. - Strong understanding of 4G/5G Radio architecture and O‑RAN ecosystem. - Experience with Git/GitHub and version control workflows. Desirable Skills - 7+ years of FPGA design experience in wireless or high‑speed systems. - Experience in high‑volume wireless products and IP development. - Contributions to standards bodies or technical forums (O‑RAN, 3GPP). About Stefanini Group Stefanini Group is a global provider of offshore, onshore and nearshore outsourcing, IT digital consulting, systems integration, application, and strategic staffing services to Fortune 1000 enterprises around the world. #J-18808-Ljbffr Apply on Kit Job: kitjob.ca/job/2p9sod