FPGA Design Verification Engineering Internship (Saskatchewan)

Enhance your engineering skills through an FPGA Design Verification Internship, specifically targeting SystemVerilog and UVM. This immersive experience will equip you with techniques to validate FPGAs effectively and efficiently. This internship provides a unique opportunity to apply your knowledge of RTL, verification plans, and test strategy development in real-world scenarios. You will be involved in comprehensive testing—functional, integration, and regression—while diagnosing issues through advanced debugging methods. Your role will include substantial interaction with cross-functional teams to support verification initiatives. Key Responsibilities: - Engage in multi-level FPGA design verification - Develop and execute comprehensive test plans - Conduct thorough regression and functional testing - Utilize waveforms for troubleshooting - Collaborate closely with design teams Requirements: - Knowledge in SystemVerilog and UVM methodologies - Proficient in RTL understanding and validation techniques - Scripting experience with Python, Tcl, or similar - Familiarity with high-speed interfaces - Critical thinking skills for requirement analysis Seize this chance to amplify your expertise in FPGA Design Verification and work in a supportive, educational setting. Apply on Kit Job: kitjob.ca/job/2osbnh