Process Re-Engineering Senior Expert (Saskatchewan)

Join our DSP team as a senior‑level Analog & Mixed‑Signal Engineer. Responsibilities Define and review system‑level analog and mixed‑signal functions for coherent optical modems. Develop behavioral models of analog and mixed‑signal blocks using C++ and SystemC, focusing on firmware register‑map interfaces, control, observability, and execution speed. Apply C++ / SystemC‑AMS to model continuous‑time and mixed‑signal behavior of PLLs, clocking systems, filters, DACs, ADCs, SerDes, and related subsystems. Build, support, and maintain C++ and MATLAB‑based verification flows, including C++ MEX wrappers that enable behavioral models to be exercised directly within system simulators. Collaborate closely with analog, digital, DSP, firmware, and lab teams to align models, specifications, and validation plans. Support ASIC lab bring‑up and characterization, correlating silicon and lab data with behavioral models and system simulations. Plan and schedule design tasks; specify required resources, tools, and processes. Create and publish design guidelines, how‑to documents, and setup guides in Confluence. Mentor junior engineers and contribute to best practices in analog behavioral modeling and system‑level validation. Qualifications Expert‑level understanding of analog and mixed‑signal processing in high‑speed communication systems. Proven experience writing C++ and/or SystemC behavioral models for hardware‑adjacent systems. Demonstrated ability to operate at the system‑architecture level while remaining grounded in real analog behavior and physical impairments. Solid understanding of key analog impairments, including noise, distortion, non‑linearity, bandwidth limitations, jitter, and phase noise, and their impact on modem‑level performance. Strong intuition for analog‑digital partitioning, power‑performance trade‑offs, and calibration strategies. Comfortable translating loosely defined system goals into well‑bounded analog architectures and specifications. Ability to mentor engineers across disciplines and serve as a technical reference for analog signal‑processing decisions. Comfortable working in a Linux‑based development environment, using Git and modern collaborative workflows. Clear technical communication skills and the ability to work effectively across disciplines. Education & Experience Post‑graduate degree in Physics or Engineering with a focus on ASIC hardware, communication systems, and/or control systems. Tools C++ SystemC‑AMS MATLAB Simulink Python Cadence Virtuoso Cadence AMS Designer Xcelium AMS Pay Range The annual salary range for this position is $109,000 – $174,000 CAD. Benefits In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans; participation in 401(K) (USA) & DCPP (Canada) with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company‑paid holidays, paid sick leave, and vacation time. Ciena also complies with all applicable laws regarding Paid Family Leave and other leaves of absence. Equal Chance Employer We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Apply on Kit Job: kitjob.ca/job/2prtg7