Design Verification Engineer At Broadcom Richmond

Join Broadcom as a Design Verification Engineer, utilizing your expertise in System Verilog and UVM to validate creative designs. Contribute to PCIe technology and engage in a agile workplace where technology evolves rapidly. We are seeking a highly skilled Design Verification Engineer to ensure the quality of new designs through constrained random methodologies. This position entails collaborating with a talented team focused on groundbreaking technology, offering opportunities for technical leadership. Candidates should have a strong background in verification skills and experience with PCIe interfaces. Key Responsibilities: • Verify new designs using constrained random methodologies • Collaborate with team members on PCIe and host interfaces • Drive coverage closure for verification completion • Utilize System Verilog and UVM in design verification • Explore leading-edge technologies across product lines Requirements: • BSEE with 8+ years or MSEE with 6+ years of experience • Proficient in System Verilog and UVM • Familiarity with PCIe and 3rd party BFMs • Solid understanding of datapath flows • Self-motivated with a collaborative spirit Utilize your skills in verification to shape innovative designs at Broadcom in a transformative technology landscape. #J-18808-Ljbffr Apply on Kit Job: kitjob.ca/job/2nhsn8