Senior Asic Design Verification Engineer Richmond

Elevate your career as a Senior ASIC Design Verification Engineer with Broadcom, focusing on advanced System Verilog and UVM methodologies. Work on pivotal projects in a highly collaborative setting. At Broadcom, we are looking for a motivated Design Verification Engineer to verify designs that will lead the technology evolution in the industry. You will engage closely with an effective group focused on PCIe technologies and contribute towards the quality assurance of cutting-edge product lines. Your extensive experience is essential for driving technical leadership in this quick-paced environment. Key Responsibilities: • Validate designs using constrained random verification techniques • Engage in team-driven verification processes • Implement coverage closure strategies for effective validation • Apply System Verilog and UVM for design testing • Collaborate on projects involving innovative technology Requirements: • BSEE + 8+ years or MSEE + 6+ years in ASIC verification • Proficient in System Verilog and UVM methodologies • Experience with PCIe and third-party BFM tools • Good understanding of datapath characteristics • Strong interpersonal and teamwork skills Enhance your impact on tomorrow's technologies as a Senior Design Verification Engineer at Broadcom, shaping the future of ASIC designs. J-18808-Ljbffr Apply on Kit Job: kitjob.ca/job/2ox8ii