Senior Asic Synthesis Engineer At Ciena Riviere Des …, Riviere-des-Prairies—Pointe-aux-Tre …

Drive frontend ASIC implementation at Ciena, a leader in high-speed connectivity. This senior role emphasizes synthesis, static timing analysis, and logical equivalence checking. At Ciena, you will contribute to the Wavelogic Digital Signal Processor programs by executing frontend designs. Your responsibilities will include synthesis, timing analysis, and validating clock domains for high-performance ASIC integration. Collaborating with various teams, you will help maintain a culture that emphasizes personal growth and impactful technology. Key Responsibilities: - Execute frontend implementation for assigned ASIC subsystems - Develop and maintain timing constraints for synthesis and signoff - Validate logical equivalence between RTL and gate-level designs - Implement engineering change orders for design iterations - Collaborate with multidisciplinary engineering teams Requirements: - B.Sc. in Electrical or Computer Engineering - Experience with ASIC synthesis and static timing analysis - Knowledge of ASIC implementation flows and RTL principles - Ability to work under project schedules - Familiarity with scripting languages for automation Leverage your expertise in synthesis and timing analysis to innovate with Ciena's advanced ASIC technologies.#J-18808-Ljbffr Apply on Kit Job: kitjob.ca/job/2ods5v